In semiconductor design, standard cell methodology is a method of designing integrated circuits (ICs) with generally uniform design blocks or elements. Standard cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology has made it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the aspect of (physical) implementation. Along with semiconductor manufacturing advances, standard cell methodology has helped designers scale ICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate system-on-a-chip (SoC) devices.
A standard cell is a group of transistors and interconnect structures that provides a Boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) or a storage or register function (e.g., a flip-flop or a latch). The simplest cells are direct representations of the elemental NAND, NOR, and XOR Boolean functions, although cells of much greater complexity are commonly used. Generally cells are designed to act as literal building blocks of predefined widths and/or heights, such that multiple cells may be arranged in a regular predictable rectangular structure.
A standard cell library is a collection of electronic logic functions of various complexity, such as NAND, NOR, flip-flops, latches, inverters, and buffers. These cells are realized as fixed-height, variable-width cells. One key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimized full-custom layouts, which minimize delays and area.
Standard cell design for field effect transistors (FET) occasionally includes Fin-FET technology. A Fin-FET includes a non-planar transistor formed with a thin silicon fin. The distance from source to drain determines the effective channel length of the device.
Such Fin-FET technology is typically burdened by many deep sub-micron stress and proximity effects. Such effects create issues such as inefficient layout and/or poor performance. For example, having breaks in patterns or continuous patterns can cause devices that neighbor these patterns to have undesired electrical characteristics that result in actual silicon results that are uncorrelated to modeled simulation. Layout area is frequently wasted because mitigation of such undesired electrical effects is accomplished with an open space distance from the pattern.